In recent years, with increased operation speed of semiconductor devices, it has become common to have a DLL circuit or PLL circuit in such a device as means of synchronizing the input/output timing of data to a system clock signal. For example, in DDR2-DRAM (Double Data Rate 2-Dynamic Random Access Memory), the DLL circuit initializes the internal circuitry with a DLL reset signal when the power source is turned on, and matches the edges of a system clock signal and an internal clock signal within two hundred cycles, thereby matching the output timing to the system clock signal.
FIG. 6 is a block diagram showing an example of a related DLL circuit. In FIG. 6, the DLL circuit 100 has a general configuration in which the rising and falling edges of system clock signals CK and CKB are independently and respectively matched to the rising and falling edges of an internal clock signal. The DLL circuit 100 comprises counters 12A and 12B for the rising edge and the falling edge respectively so as to independently and respectively lock up to the rising and falling edges of the system clock signals CK and CKB. The counters 12A and 12B are used to determine the delay amounts of delay lines 3A and 3B respectively. The counters 12A and 12B respectively output the lower bits of their counter values to DA converters 13A and 13B, and output the remaining higher bits to shift registers 15A and 15B respectively. The DA converters 13A and 13B are used to perform fine adjustment of the internal delay time of the DLL circuit 100, and the shift registers 15A and 15B are used to perform coarse adjustment of the internal delay time of the DLL circuit 100. When the duty ratio of the system clock signals CK and CKB is 50%, the counter values of the shift register 15A for the rising edge and the shift register 15B for the falling edge are approximately the same.
When the DLL circuit 100 receives a reset signal RST, the counters 12A and 12B are initialized and the DLL circuit 100 starts a lock-up sequence. On the rising edge side, a first-stage circuit 2A receives the system clock signals CK and CKB, and it outputs a signal S1A to the delay line 3A. The delay line 3A is a delay circuit that performs coarse adjustment, and it outputs signals S2A and S3A having a delay amount determined by the counter value of the shift register 15A for the rising edge to a phase synthesis circuit 4A in the following stage. There is a slight difference in delay length between the signals S2A and S3A. The phase synthesis circuit 4A synthesizes these two signals S2A and S3A at a ratio specified by the DA converter 13A and outputs a signal S4A. In other words, the phase synthesis circuit 4A is used to perform fine adjustment (tuning) of the phase.
Similarly, on the falling edge side, a first-stage circuit 2B receives the system clock signals CK and CKB, and it outputs a signal S1B to the delay line 3B. The delay line 3B outputs signals S2B and S3B having delay amounts determined by the counter value of the shift register 15B for the falling edge to a phase synthesis circuit 4B in the following stage. The phase synthesis circuit 4B synthesizes these two signals S2B and S3B at a ratio specified by the DA converter 13B and outputs a signal S4B.
A clock synthesis circuit 5 synthesizes the signals S4A and S4B. A buffer 6 buffers a signal S5 synthesized by the clock synthesis circuit 5, and outputs it as signals S6 and S8 to DQ7 and a dummy DQ8. DQ7 outputs a signal D0 to the outside, and the dummy DQ8 outputs a signal S9A, which is the same signal as the signal D0, and its inverted signal S9B to phase comparator circuits 9A and 9B respectively.
On the rising edge side of the system clock signal CK, the phase comparator circuit 9A compares the phases of the system clock signal CK and the signal S9A in order to align the phases of the system clock signal CK and the signal S9A outputted from the dummy DQ8, and operates a control circuit 11A so that the counter value of the counter 12A continues to increase (increment) until the rising edge of the system clock signal CK is detected. Because of this, the signal S9A is delayed until it is matched with the system clock signal CK.
Similarly, on the falling edge side, the phase comparator circuit 9B compares the phases of the system clock signal CKB and the signal S9B in order to align the phases of the system clock signal CKB and the signal S9B outputted from the dummy DQ8, and operates a control circuit 11B so that the counter value of the counter 12B continues to increase (increment) until the falling edge of the system clock signal CKB is detected. Because of this, the signal S9B is delayed until it is matched with the system clock signal CKB. Hereinafter, mainly the rising edge side will be described.
FIG. 7 is a timing chart showing the phase relationship between the system clock signal CK and the signal S9A during normal operation of the related DLL circuit shown in FIG. 6. A waveform A in FIG. 7 shows the waveform of the signal S9A, delayed from the system clock signal CK by the amount specific to the DLL circuit, when the counter 12A is initialized with a DLL reset. The DLL circuit 100 increases (increments) the value of the counter 12A so that the rising edge of the signal S9A is aligned with an edge P of the system clock signal CK. The waveform of the signal S9A changes from the waveform A to a waveform B in FIG. 7 when the counter value of the counter circuit 12A is increased (incremented). The rising edge of the waveform B has not yet reached the rising edge P of the system clock signal CK, therefore the counter value is increased (incremented) even more to result in a waveform C. When in the state of the waveform C, since the rising edge P of the system clock signal CK has been detected, the counter value is decreased (decremented) so that the rising edge P of the system clock signal CK is redetected again. Finally, as indicated by a waveform D, the rising edge P of the system clock signal CK is matched with the rising edge of the signal S9A.
At DLL reset, the DLL circuit 100 operates as described above, and matches the edges of the system clock signal CK and the signal S9A, which is an internal clock signal, thereby matching the output timing of the signal S9A to the system clock signal CK. Further, the edges of the system clock signal CKB and the signal S9B, which is another internal clock signal, are matched, thereby matching the output timing of the signal S9B to the system clock signal CKB.
As a related technology, a CPU reset circuit capable of preventing a malfunction at startup is disclosed in Patent Document 1. This CPU reset circuit generates a CPU history signal that determines whether the CPU is operating normally, and resets the CPU with the CPU history signal when the CPU malfunctions.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-8-263177.